Analog Input-Output Board by PC Designs

©Roy Cleveland 2000-2003
  This is the completed AIO assembly designed for Arius, Inc. in Frederick, Maryland. It plugs into the DSP Mainboard and receives control signals from one of the FPGAs mounted on the board. The two integrated circuits in the foreground are the CP Clare LiteLink® IC set. They provide a full Direct Access Arrangement (DAA) for both domestic and international loop current and impedance matching. The auxillary IC provides ring detection for a secondary channel. When used with the Telephony Interface board, described elsewhere, the DAA can switch to the line that generates the ring signal.

The circuitry was designed by PC Designs under the direction of Arius, Inc. Prototype boards were assembled by both Mark Space and PC Designs. Testing was done by PC Designs.
This is an underside view of the AIO showing the fuses, Tranzorb® and the connectors that allow it to snap into the DSP board. The fuses and Tranzorb are located on the right corner in this view. This board was made in four layers, with the plane layers positioned internally. The oval cutout prevents solder from bridging the isolated and non-isolated areas of the board. In order to meet certain requirements, this gap (known as creepage distance) must be a minimum of 3 millimeters. The AIO meets these requirements. The large package in the center is the FET switch that brings the DAA off hook.  
  During testing, it was discovered that the preliminary circuitry supplied by CP Clare, would reset during certain ring conditions. The problem was traced to a voltage dropout during part of the ring cycle when the DAA was taken off-hook. To solve the problem, a diode "hold-up" circuit was installed. This view shows the placement of the diode between the two ICs. Once the modification was done, the unit was re-tested and passed.
 

Below is part of the schematic for the AIO board. The complete circuit consists of a Direct Access Arrangement (DAA), and an AC97 serial CODEC. Shown is the DAA section, designed using the LiteLink™ chipset from C.P. Clare. The circuit is designed to provide impedance matching and meet the safety requirements of UL 1950, FCC Part 47, European CTR-21, as well as Australian Telephone (Austel). The design supports a second ring channel, caller ID enabling, as well as the usual functions of ring detect and off-hook control.

 
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